Why do this
The idea of building a Z80 second processor to BBC micro came from when I bought a Torch Z80 card from Ebay to my BBC micro.
Looking at the solution, it did not use the Tube ULA, only 2 IO chips, one for each side of the bridge. My thought was there must be an easier way to implement this.
That is why I started with this project and got one on my friends Jan-Erik to help with coding.
Hardware and software is Open Source and schematic and PCB layout can be found at EasyEDA.
When ready I will offer the board with and without component to cost price. Feel free to email me if you have a question or want to have the board now. firstname.lastname@example.org
How to do this
The principle to replace the Tube ULA is very simple, Using 2 latches to store data they should be transfer from each CPU.
Adding some circuity to support interrupt and busy flag and you have a working system.
It is not as fast as the ULA, but it will work with a decent speed. (To be tested)
I call the tube design a mini tube and will be included in coming designs.
It will use a serial tube protocol, may be based on work found on this page http://mdfs.net/Software/Tube/Serial/
It dependence on the speed we get for transfer.
Testing done so far with a simpler protocol give a refresh rate on the screen about 50-100 frames.
Way faster then other system.
One of the reason for this speed is that we do not share memory with video chips. This is common to do in most populare Z80 machines in the 80’s like Amstrad, Commodore 128, ZX Spectrum to mansion some of them.
Another reason is that the BBC is doing all the screen calculations.
The card can handle Z80 CPU up to 50 MHz zero wait but the fastest 40pin z80 is 20Mhz.
The system will handle 512Kbyte RAM and CPM 2.X and 3.X and run all software for CPM including for BBC CPM.
It will also handle GSX library so it will work for games.
It will work on much more OS and software that you like to exprimet with.
Addresses and mini protocol
Address list from BBC side
FEE0 – read status register bit6=Interrupt Status, bit7= Busy Status
FEE8 – Write byte to Z80 and set interrupt
FEF0 – Read byte from Z80 and clear interrupt
FEf0 – Set/Clear busy Status. Set by data bit 7. Busy=1
nb: reason to have this gaps in the address range is for the original tube to not try to initialize. May be changed in final release.
Address list from Z80 side
xxx0 – read status register bit6=Interrupt Status, bit7= Busy Status
xxx1 – Write byte to Z80 and set interrupt
xxx2 – Read byte from Z80 and clear interrupt
xxx3 – Set busy Status and bank switch.
- Busy status are set by data bit 6=1
- Bit 0-3 are bank selector
- 3210 bit
- 0000 = Enable ROM and top 16K Hi RAM. This is reset default status
- 1000 = Disable ROM. Select RAM bank 0 and 16K Hi RAM
- 1001 = Disable ROM. Select RAM bank 1 and 16K Hi RAM
- 1010 = Disable ROM. Select RAM bank 2 and 16K Hi RAM
- 1111 = Disable ROM. Select RAM bank 7 and 16K Hi RAM
- Bit 6,7 are user programmable LED’s 0=Light
When booting or hardware reset the flip-flops the control the busy signal for both side of the bridge is set to busy.
When the Z80 has done it init code, it set it to no busy (0).
The BBC side stays busy until the user activates the Z80 module. *SweetZ80
The Z80 does not push any data to the BBC side before the busy signal is cleared.
Sending data to the other side
Sending data to the other side is done by writing a byte to xxx1. An interrupt is automatic generated and will be held low until the byte is read from the other side.
The data sent to the BBC represent OS call.
When starting a transfer, care should be take not to start transferring data while the opposite side is transferring.
A transfer need to end with a zero byte.
|# of byte to send inc null byte||Data0
|Data 1||Data 2||Data 3||Data 4||Data 5||Data 6|
Table of OS call.
Init load of OS and BIOS
There is build in an command to load software direct into the z80 memory map.
With this function you can create your own images that you want to upload into the Z80 system.
The limit is 32Kbyte and is in the upper part of the memory.
This mean you need to create an image the switch off the boot ROM to take advance of a full system.
The sequence for this upload is